Principles and Practice of Marketing.
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Most popular etextbook sub-categories. Search by book title, ISBN or author. The use of the rapid thermal annealer RTA provides good activation while limiting the time at elevated temperatures to less than a few minutes to minimze the movement of the dopants due to diffusion. A two step RTA process as disclosed in U. A A thick layer of resistive material such as cermet CrSiO2 is sputtered onto the nitride , annealed using the rapid thermal annealer, and patterned to form required resistors.
Following the etch a wet chemical clean-up is used which maintains photoresist intact. Using a rapid thermal annealing process, the contact metal is annealed at C. This forms NPN base contacts , PNP collector contact and emitter contact , N-channel backgate contact and gate contact , and P-channel source contact and drain contact The temperature used for the contact anneals and cermet anneals are sufficiently low temperature that the implant damage used to convert the field area to semi-insulating is not annealed out. If higher anneal temperatures are needed for other metalization systems or resistor materials, the boron damaging implant can be delayed in the process until after all the heat cycles have been completed.
Titanium followed by platinum and gold is deposited and lifted off using the previously described process. No contact anneal is used for the case of the Schottky diodes. To isolate the various transistors, a narrow micron wide moat trench will be etched through the various epi layers into the semi-insulating GaAs substrate completely encirculing each of the transistors. Note: More than one transistor can be placed inside the same moat to save area if the transistors do not need to be electrically isolated from each other.
The trench is then filled in with nitride so that metal interconnect can be used to connect the various transistors together into the required circuit. This trench process may accomplished in the following manner. A layer of aluminum is then deposited. Using photoresist the trench mask is patterned over the aluminum. The back side of the layered substrate is protected and the aluminum is etched from the trench region.
The exposed nitride typically A thick is plasma etched from the trench region. Using the photoresist as a mask the exposed GaAs is ion milled to a depth typically The resist is then removed. This nitride is ion milled at 75 degrees off axis to remove the nitride from the aluminum surface.
This process yields only a partially planarized surface and the trench is only partially filled. The aluminum layer acts as an etch stop which prevents the underlying nitride from being etched during the RIE etch process. After two repetitions of this process the surface is essentially planar. After the planarization process the aluminum is stripped from the layered substrate.
Photoresist is patterned and the first vias are etched down to the ohmic metal. From this point on a standard two-level metal process is used to complete the fabrication of the required circuits. This concludes the description of the first preferred embodiment process. Doping levels and film thicknesses specified are typical and variations of the parameters in order to optimize the process for a specific application are included modifications.
The second preferred embodiment method uses a grown base for the NPN transistor and includes the following steps as illustrated in cross sectional elevation view in FIGS. In lieu of this implantation process the starting material for the second preferred embodiment includes a top P-type doped GaAs layer as illustrated in FIG. This etch depth is not critical and some overetching into the N-type layers is performed to insure that all of the exposed P-type layers are removed and that the remaining exposed GaAs surface is composed of only N-type GaAs This etch provides permanent alignment marks for subsequently aligning the remaining photoresist levels.
Afterwards the first preferred embodiment method is followed starting with step d as illustrated in FIGS. A third preferred embodiment method provides a PNP transistor for applications in which very low collector resistance is needed for the PNP transistors which are to be integrated with NPN transistors, and includes an additional epi deposition.
This option may be attractive in cases in which a high energy P-type dopant implant process is not available for forming the PNP collector regions as in the first and second preferred embodiment methods. The method includes the following steps:.
The thickness of the epi layer would be determined by the required NPN collector sheet resistance. This implant would be activated during the subsequent epi deposition converting these regions into heavily doped P-type GaAs. This second epi deposition will include an N-epi region similiar to that of layer of the second preferred method plus, depending on whether a grown NPN base as the second preferred embodiment method or an implanted NPN base process as in the first preferred embodiment method is used, a P-type base layer similiar to that of layer may be deposited.
The process then proceeds as outlined in steps d - t of the first preferred embodiment or steps b - c of the second preferred embodiment. This simplifies the isolation process which would consist of a damage implant outside of the regions in which the active transistors are to be fabricated. The fourth preferred embodiment method includes the following steps with only the NPN illustrated for clarity although the other three device types can be included as previously described :.
After cleaning the substrate a thin layer of silicon nitride or other dielectric material is deposited onto the surface. The substrate is then patterned with photoresist and the nitride layer is selectively removed from regions in which the alignment marks are to be formed. The only areas which are etched are those in which a pattern exists in the NPN collector level which is nested inside the holes previously etched in the nitride level see step a above.
These patterns etched in the GaAs provide permanent alignment marks allowing subsequent levels to be aligned to the NPN collector. These alignment marks could be incorporated in other levels such as the PNP collector with appropriate process changes to make it possible to align critical geometries to the most critical level. After etching the alignment marks the photoresist is stripped; the alignment marks are not illustrated.
This implant could be activated during the subsequent epi deposition converting these regions into heavily doped P-type GaAs. This second epi deposition will include an N- epi region similiar to layer in the second preferred embodiment plus, depending on whether an implanted NPN base process as described in the first preferred embodiment method or a grown NPN base as in the second preferred embodiment method is used, a P-type base layer similiar to layer of the second preferred embodiment method may be deposited.
The process then proceeds essentially as outlined in the first preferred embodiment method starting with step b. See FIGS. The trench isolation can be omitted for process simplification. The fourth preferred embodiment would require a total of two epi depositions: one for depositing the NPN N- collector region; and one for depositing the emitter layers. The first, second, and fourth preferred embodiment methods require two epi depositions.
The first epi layer is deposited after the formation of the heavily doped collector regions. The second epi layer is deposited after the formation of the base by either implanting as described in the first preferred embodiment method or selectively etched as outlined in the second preferred embodiment method. In an effort to reduce the number of epi deposition steps the fifth preferred embodiment method offers a process in which only one epi deposition is required as follows:.
Thin buffer regions in which the aluminum concentration is graded between that used in the AlGaAs and zero can be used between the various transistions from GaAs to AlGaAs and back.
This etch results in a mesa structure in which the NPN base and emitter contacts are on the top level while the NPN collector contact is made at a lower level. The nitride is then stripped from the wafers and a new plasma nitride layer is deposited with a typical thickness of A.
No trench process as described in steps s - s. The wafers are then processed through the interconnect levels as described briefly in step t which completes the process.
Wet Etching Cleaning and Passivation. Mora, C. Semiconductor integrated circuit including opposed substrates of different semiconductor materials and method of manufacturing the semiconductor integrated circuit. The processing challenges, including topography and film stress, are overcome using methods similar to those used in the SUMMiTTM Process: topography issues are mitigated by using Chemical-Mechanical Polishing CMP to achieve planarization, and stress is maintained at low levels using a proprietary process. Phase diagrams and crystal growth. Notify me.
The sixth preferred embodiment method uses an AlGaAs layer as a sacrificial layer for controlling the NPN base profile and as a cap layer for the implanted base anneal. In lieu of the use of a nitride layer as the sacrificial layer to determine the location of the base implant profile as in steps b and c of the first preferred embodiment method, an additional layer of Al x Ga 1-x As could be deposited during the initial epi growth step. The thickness of this Al x Ga 1-x As layer would be adjusted along with the implant dose and energy to yield the desired doping profile for the NPN base.
The Al x Ga 1-x As layer would also act as the cap layer for the implant anneal.
This approach has the advantage over the use of nitride in that the thermal properties of Al x Ga 1-x As better match that of GaAs than those of nitride and should produce less strain. Additionally, the Al x Ga 1-x As would maintain an arsenic rich surface in contact with the base layer during the initial processing.